Chandrasekhar, Arun ; Stoukatch, Serguei ; Brebels, S. ; Balachandran, Jayaprakash ; Beyne, Eric ; De Raedt, W. ; Nauwelaers, Bart ; Poddar, Anindya (2003) Characterisation, Modelling and Design of Bond-Wire Interconnects for Chip-Package Co-Design Insertion Loss (dB). In: Gallium Arsenide applications symposium. GAAS 2003, 6-10 October 2003, Munich.
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Abstract
This work is a comprehensive experimental investigation of chip to package wirebond interconnects for chip-package co-design. Wirebonds are interconnect bottlenecks in RF design, but are difficult to avoid due to their low cost and manufacturing ease. We have shown measurements on wirebonds in coplanar configuration with different return paths and also the cross coupling. We have also extracted lumped and distributed models and demonstrate the excellent agreement with measurements atleast upto 15GHz. We have proposed multi-wirebonds as a potential solution for better impedance matching. Different types of inductors with Q-factors of upto 100 have also been illustrated. We show influence of encapsulant on wirebonds and finally we also demonstrate a methodology to extract the time-domain response from S-parameters.
| Document type: | Conference or Workshop Item (Paper) |
|---|---|
| Subjects: | Area 09 - Ingegneria industriale e dell'informazione > ING-INF/01 Elettronica |
| Depositato da: | CIB Staff |
| Depositato il: | 17 Jun 2004 |
| Last modified: | 16 May 2011 13:32 |
Solo per lo Staff dell Archivio: Gestione del documento

