Abstract

This paper deals with an original design of an active power splitter featuring a differential output presenting a greatly enhanced even mode rejection.The proposed circuit consists in two cascaded common emitter and common collector differential pairs.For achieving the best performance,it is shown that each of these two differential pairs requires a specific common node to ground impedance that is discussed.The circuit has been implemented on a 0.25 µm SiGe BiCMOS process and exhibits anticipated phase and amplitude broadband unbalance less than 6.5 ° and 0.6 dB respectively all over the 6 -27 GHz frequency range.At 20 GHz,a common mode rejection ratio better than 43 dB is predicted,i.e.a maximum 0.12 dB /0.35 ° output signal unbalance.