Abstract

We propose transmission line pulse (TLP) stress instead of DC bias stress in order to stimulate different failure mechanisms for HBTs for wafer level reliability characterisation and show the effects of degradation on the device performance. The established Wunsch-Bell model [1] is employed for a calculation of the intrinsic device temperatures within the active region from the measured pulse voltage and current. The device MTTF can be predicted for various thermally induced failure modes. Additional degradation mechanisms related to the high current densities obtained during TLP stress show that this method is more operational than the established accelerated lifetime tests.